DRAMSim2 - A cycle accurate DRAM simulator modified for row-buffer caching

Zhao Zhang, Zhichun Zhu & Xiaodong Zhang
Reproducibility experimentation for "A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality" that uses a modified DRAMSim2 to simulate SPEC CPU benchmarks with an interleaved row-buffer addressing scheme.
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