Dynamic programming in faulty memory hierarchies (cache-obliviously)

Saverio Caminiti, Irene Finocchi, Emanuele G. Fusco & Francesco Silvestri
Random access memories suffer from transient errors that lead the logical state of some bits to be read differently from how they were last written. Due to technological constraints, caches in the memory hierarchy of modern computer platforms appear to be particularly prone to bit flips. Since algorithms implicitly assume data to be stored in reliable memories, they might easily exhibit unpredictable behaviors even in the presence of a small number of faults. In this...