Instructor Selector Generation from Architecture Description

Miloslav Trmac, Adam Husar, Jan Hranac, Tomas Hruska & Karel Masarik
We describe an automated way to generate data for a practical LLVM instruction selector based on machine-generated description of the target architecture at register transfer level. The generated instruction selector can handle arbitrarily complex machine instructions with no internal control flow, and can automatically find and take advantage of arithmetic properties of an instructions, specialized pseudo-registers and special cases of immediate operands.