Wire delay effects reduction techniques and topology optimization in NUCA based CMP systems

Francesco Panicucci
One of the most important issues designing large last level cache in a CMP system is the increasing effect of wire delay problem which affects the banks access time and reduces the performances. Some CMP systems adopt a shared L2 cache to maximize cache capacity, instead other architectures use private L2 caches, replicating data to limit the delay from slow on-chip wires and minimize cache access time. Ideally, to improve performance for a wide variety...