Logic Level and Fault Simulation on the Rp3 Parallel Processor

Stephen Unger
Logic level simulation for circuits of the sizes currently being designed is indeed a formidable computational task. Chips are being but it today containing over a million gates, with storage elements and RAMs. Ordinary logic simulation of systems of this size can take many hours of computation time on the fastest computers. Fault simulation for such large chips, is out of the question for anything but the largest supercomputer. Certainly this is a task justifying...
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