The Benefits of Using Clock Gating in the Design of Networks-on-Chip

Michele Petracca & Luca Carloni
Networks-on-chip (NoC) are critical to the design of complex multi-core system-on-chip (SoC) architectures. Since SoCs are characterized by a combination of high performance requirements and stringent energy constraints, NoCs must be realized with low-power design techniques. Since the use of semicustom design flow based on standard-cell technology libraries is essential to cope with the SoC design complexity challenges under tight time-to-market constraints, NoC must be implemented using logic synthesis. In this paper we analyze the...
This data repository is not currently reporting usage information. For information on how your repository can submit usage information, please see our documentation.